1. Field of the Invention
The present invention relates to a semiconductor device characteristic simulation apparatus and its method, and is suitably applied to, for example, a semiconductor device characteristic simulation apparatus and its method for estimating and analyzing performance characteristics of a semiconductor integrated circuit constituted by connecting such circuit devices as a transistor to a semiconductor substrate.
2. Description of the Related Art
A conventional semiconductor integrated circuit represents a semiconductor device in which electronic circuits are constituted like a matrix by setting necessary components such as a transistor, a diode, a resistor, and a capacitor on a silicon substrate (a wafer) and interconnecting the components. For example, in a fabrication process of a semiconductor integrated circuit by forming metal oxide semiconductor (MOS) transistors on the entire surface of a wafer like a matrix, a fluctuation exists in each data of dimensions including a gate length, oxide film thickness, and implanted number of ions (hereinafter, these processing factors under fabrication are referred to as process parameters) of a MOS transistor formed by applying predetermined types of processing to the surface of the wafer.
A simulation apparatus and simulation software are developed for estimating and analyzing the fluctuation in device characteristic values of a MOS transistor formed on the surface of a wafer (what the device characteristic value denotes in this case is a voltage applied to the gate portion of the transistor so that a drain current with a certain value starts to flow. Such voltage is hereinafter referred to as threshold voltage Vth), and, moreover, checking the electric current distribution.
Therefore, this type of simulation apparatus calculates (simulates) a fluctuation in device characteristic values (the fluctuation in threshold voltages Vth) of MOS transistors which are fabricated with varying measurement data on each process parameter such as a gate length, oxide film thickness and implanted number of ions, and graphs out the calculation in normal distribution curves. Thereby, when a MOS transistor is formed on the surface of a wafer with a fluctuation in measurement data of process parameters, a user reads the device characteristic values of the transistor from the graph obtained thus.
The aforesaid simulation apparatus can display the fluctuation in device characteristic values in the form of a table or a graph when a MOS transistor is formed on the surface of a wafer and each process parameter fluctuates in accordance with a normal distribution. However, the said apparatus have neither a function for displaying the distribution of the fluctuation in each process parameter in accordance with fluctuating measurement data of process parameters under a fabrication process, nor a function for image-displaying the distribution of the fluctuation in device characteristic values on the surface of the actual wafer.